Comparison of ARM processors
This is a comparison of ARM instruction set architecture application processor cores designed by Arm Holdings (ARM Cortex-A ) and 3rd parties. It does not include ARM Cortex-R , ARM Cortex-M , or legacy ARM cores.
ARMv7-A
This is a table comparing 32-bit central processing units that implement the ARMv7-A [ 1] instruction set architecture and mandatory or optional extensions of it, the last AArch32 .
Core
Decode
Execution
Pipeline Out-of-order execution FPU Pipelined
FPU
NEON big.LITTLE Virtualization[ 2]
Process L0
L1
L2
Core
SpeedDMIPS )
ARM part number
ARM Cortex-A5
1
8
No
VFPv4 (optional)
16 × 64-bit
64-bit wide (optional)
No
No
40/28 nm
4–64 KiB / core
1, 2, 4
1.57
0xC05
ARM Cortex-A7
2
5[ 3]
8
No
VFPv4
Yes
16 × 64-bit
64-bit wide
LITTLE
Yes[ 4]
40/28 nm
8–64 KiB / core
up to 1 MiB (optional)
1, 2, 4, 8
1.9
0xC07
ARM Cortex-A8
2
2[ 5]
13
No
VFPv3
No
32 × 64-bit
64-bit wide
No
No
65/55/45 nm
32 KiB + 32 KiB
256 or 512 (typical) KiB
1
2.0
0xC08
ARM Cortex-A9
2
3[ 6]
8–11[ 7]
Yes
VFPv3 (optional)
Yes
(16 or 32) × 64-bit
64-bit wide (optional)
Companion Core
No[ 7]
65/45/40/32/28 nm
32 KiB + 32 KiB
1 MiB
1, 2, 4
2.5
0xC09
ARM Cortex-A12
2
11
Yes
VFPv4
Yes
32 × 64-bit
128-bit wide
No[ 8]
Yes
28 nm
32–64 KiB + 32 KiB
256 KiB, to 8 MiB
1, 2, 4
3.0
0xC0D
ARM Cortex-A15
3
8[ 3]
15/17-25
Yes
VFPv4
Yes
32 × 64-bit
128-bit wide
big
Yes[ 9]
32/28/20 nm
32 KiB + 32 KiB per core
up to 4 MiB per cluster, up to 8 MiB per chip
2, 4, 8 (4×2)
3.5 to 4.01
0xC0F
ARM Cortex-A17
2[ 10]
11+
Yes
VFPv4
Yes
32 × 64-bit
128-bit wide
big
Yes
28 nm
32 KiB + 32 KiB per core
256 KiB, up to 8 MiB
up to 4
4.0
0xC0E
Qualcomm Scorpion
2
3[ 11]
10
Yes (FXU&LSU only)[ 12]
VFPv3
Yes
128-bit wide
No
65 /45 nm
32 KiB + 32 KiB
256 KiB (single-core)
1, 2
2.1
0x00F
Qualcomm Krait [ 13] 3
7
11
Yes
VFPv4[ 14]
Yes
128-bit wide
No
28 nm
4 KiB + 4 KiB direct mapped
16 KiB + 16 KiB 4-way set associative
1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core)
2, 4
3.3 (Krait 200)
0x04D
Swift
3
5
12
Yes
VFPv4
Yes
32 × 64-bit
128-bit wide
No
32 nm
32 KiB + 32 KiB
1 MiB
2
3.5
?
Core
Decode
Execution
Pipeline Out-of-order execution
FPU
Pipelined
FPU
NEON big.LITTLE Virtualization[ 2]
Process
L0
L1
L2
Core
SpeedDMIPS )
ARM part number
ARMv8-A
This is a table of 64 /32-bit central processing units that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD ) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.
Company
Core
Released
Revision
Decode
Pipeline Out-of-order
Branch
big.LITTLE role
Exec.
SIMD
Fab nm )
Simult. MT
L0 cache
L1 cache Instr + Data KiB )
L2 cache
L3 cache
Core
Speed per core (DMIPS/ [ note 1]
Clock rate
ARM part number (in the main ID register)
Have it
Entries
ARM
Cortex-A32 (32-bit) [ 15] 2017
ARMv8.0-A(only 32-bit )
2-wide
8
No
0
?
LITTLE
?
?
28[ 16]
No
No
8–64 + 8–64
0–1 MiB
No
1–4+
2.3
?
0xD01
Cortex-A34 (64-bit) [ 17] 2019
ARMv8.0-A(only 64-bit )
2-wide
8
No
0
?
LITTLE
?
?
?
No
No
8–64 + 8–64
0–1 MiB
No
1–4+
?
?
0xD02
Cortex-A35 [ 18] 2017
ARMv8.0-A
2-wide[ 19]
8
No
0
Yes
LITTLE
?
?
28 / 16 /
No
No
8–64 + 8–64
0 / 128 KiB–1 MiB
No
1–4+
1.7[ 20]
?
0xD04
Cortex-A53 [ 21] 2014
ARMv8.0-A
2-wide
8
No
0
Conditional+
big/LITTLE
2
?
28 / 20 /
No
No
8–64 + 8–64
128 KiB–2 MiB
No
1–4+
2.24[ 22]
?
0xD03
Cortex-A55 [ 23] 2017
ARMv8.2-A
2-wide
8
No
0
big/LITTLE
2
?
28 / 20 /[ 24]
No
No
16–64 + 16–64
0–256 KiB/core
0–4 MiB
1–8+
2.65[ 25]
?
0xD05
Cortex-A57 [ 26] 2013
ARMv8.0-A
3-wide
15
Yes
?
?
big
8
?
28 / 20 /[ 27]
No
No
48 + 32
0.5–2 MiB
No
1–4+
4.1[ 20]
?
0xD07
Cortex-A65 [ 28] 2019
ARMv8.2-A(only 64-bit )
2-wide
10-12
Yes
Two-level
?
9
?
SMT2
No
32–64 + 32–64 KiB
0, 64–256 KiB
0, 0.5–4 MiB
1-8
?
?
0xD06
Cortex-A65AE [ 29] 2019
ARMv8.2-A
?
?
Yes
Two-level
?
2
?
SMT2
No
32–64 + 32–64 KiB
64–256 KiB
0, 0.5–4 MiB
1–8
?
?
0xD43
Cortex-A72 [ 30] 2015
ARMv8.0-A
3-wide
15
Yes
Two-level
big
8
28 / 16
No
No
48 + 32
0.5–4 MiB
No
1–4+
4.7[ 22] [ 31]
?
0xD08
Cortex-A73 [ 32] 2016
ARMv8.0-A
2-wide
11–12
Yes
Two-level
big
7
28 / 16 / 10
No
No
64 + 32/64
1–8 MiB
No
1–4+
4.8[ 20] [ 31]
?
0xD09
Cortex-A75 [ 23] 2017
ARMv8.2-A
3-wide
11–13
Yes
Two-level
big
8?
2*128b
28 / 16 / 10
No
No
64 + 64
256–512 KiB/core
0–4 MiB
1–8+
6.1[ 20] [ 31]
?
0xD0A
Cortex-A76 [ 33] 2018
ARMv8.2-A
4-wide
11–13
Yes
128
Two-level
big
8
2*128b
10 / 7
No
No
64 + 64
256–512 KiB/core
1–4 MiB
1–4
6.4
?
0xD0B
Cortex-A76AE [ 34] 2018
ARMv8.2-A
?
?
Yes
128
Two-level
big
?
?
No
No
?
?
?
?
?
?
0xD0E
Cortex-A77 [ 35] 2019
ARMv8.2-A
4-wide
11–13
Yes
160
Two-level
big
12
2*128b
7
No
1.5K entries
64 + 64
256–512 KiB/core
1–4 MiB
1–4
7.3[ 20] [ 36]
?
0xD0D
Cortex-A78 [ 37] [ 38] 2020
ARMv8.2-A
4-wide
Yes
160
Yes
big
13
2*128b
No
1.5K entries
32/64 + 32/64
256–512 KiB/core
1–4 MiB
1–4
7.6-8.2
?
0xD41
Cortex-X1 [ 39] 2020
ARMv8.2-A
5-wide[ 39]
?
Yes
224
Yes
big
15
4*128b
No
3K entries
64 + 64
up to 1 MiB[ 39]
up to 8 MiB[ 39]
custom[ 39]
10-11
?
0xD44
Apple
Cyclone [ 40] 2013
ARMv8.0-A
6-wide[ 41]
16[ 41]
Yes[ 41]
192
Yes
No
9[ 41]
28[ 42]
No
No
64 + 64[ 41]
1 MiB[ 41]
4 MiB[ 41]
2[ 43]
?
1.3–1.4 GHz
Typhoon
2014
ARMv8.0‑A
6-wide[ 44]
16[ 44]
Yes[ 44]
Yes
No
9
20
No
No
64 + 64[ 41]
1 MiB[ 44]
4 MiB[ 41]
2, 3 (A8X)
?
1.1–1.5 GHz
Twister
2015
ARMv8.0‑A
6-wide[ 44]
16[ 44]
Yes[ 44]
Yes
No
9
16 / 14
No
No
64 + 64[ 44]
3 MiB[ 44]
4 MiB[ 44] A9X )
2
?
1.85–2.26 GHz
Hurricane
2016
ARMv8.0‑A
6-wide[ 45]
16
Yes
"big" (In A10 /A10X paired with "LITTLE" Zephyr
9
3*128b
16 (A10 )A10X )
No
No
64 + 64[ 46]
3 MiB[ 46] A10 )A10X )
4 MiB[ 46] A10 )A10X )
2x Hurricane (A10) Hurricane (A10X)
?
2.34–2.36 GHz
Zephyr
ARMv8.0‑A
3-wide
12
Yes
LITTLE
5
16 (A10 )A10X )
No
No
32 + 32[ 47]
1 MiB
4 MiB[ 46] A10 )A10X )
2x Zephyr (A10) Zephyr (A10X)
?
1.09–1.3 GHz
Monsoon
2017
ARMv8.2‑A[ 48]
7-wide
16
Yes
"big" (In Apple A11 paired with "LITTLE" Mistral
11
3*128b
10
No
No
64 + 64[ 47]
8 MiB
No
2x Monsoon
?
2.39 GHz
Mistral
ARMv8.2‑A[ 48]
3-wide
12
Yes
LITTLE
5
10
No
No
32 + 32[ 47]
1 MiB
No
4× Mistral
?
1.19 GHz
Vortex
2018
ARMv8.3‑A[ 49]
7-wide
16
Yes
"big" (In Apple A12 /Apple A12X /Apple A12Z paired with "LITTLE" Tempest
11
3*128b
7
No
No
128 + 128[ 47]
8 MiB
No
2x Vortex (A12) Vortex (A12X/A12Z)
?
2.49 GHz
Tempest
ARMv8.3‑A[ 49]
3-wide
12
Yes
LITTLE
5
7
No
No
32 + 32[ 47]
2 MiB
No
4x Tempest
?
1.59 GHz
Lightning
2019
ARMv8.4‑A[ 50]
8-wide
16
Yes
560
"big" (In Apple A13 paired with "LITTLE" Thunder
11
3*128b
7
No
No
128 + 128[ 51]
8 MiB
No
2x Lightning
?
2.65 GHz
Thunder
ARMv8.4‑A[ 50]
3-wide
12
Yes
LITTLE
5
7
No
No
96 + 48[ 52]
4 MiB
No
4x Thunder
?
1.8 GHz
Firestorm
2020
ARMv8.4-A[ 53]
8-wide[ 54]
Yes
630[ 55]
"big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
14
4*128b
5
No
192 + 128
8 MiB (A14)
No
2x Firestorm (A14) Firestorm (M1) 6x or 8x Firestorm (M1 Pro)Firestorm (M1 Max)
?
3.0–3.23 GHz
Icestorm
ARMv8.4-A[ 53]
4-wide
Yes
110
LITTLE
7
2*128b
5
No
128 + 64
4 MiB
No
4x Icestorm (A14/M1) Icestorm (M1 Pro/Max)
?
1.82–2.06 GHz
Avalanche
2021
ARMv8.6‑A[ 53]
8-wide
Yes
"big" (In Apple A15 and Apple M2/M2 Pro/M2 Max/M2 Ultra paired with "LITTLE" Blizzard
14
4*128b
5
No
192 + 128
12 MiB (A15)
No
2x Avalanche (A15) Avalanche (M2) Avalanche (M2 Pro)8x Avalanche (M2 Max)Avalanche (M2 Ultra)
?
2.93–3.49 GHz
Blizzard
ARMv8.6‑A[ 53]
4-wide
Yes
LITTLE
8
2*128b
5
No
128 + 64
4 MiB
No
4x Blizzard
?
2.02–2.42 GHz
Everest
2022
ARMv8.6‑A[ 53]
8-wide
Yes
"big" (In Apple A16 paired with "LITTLE" Sawtooth
14
4*128b
5
No
192 + 128
16 MiB
No
2x Everest
?
3.46 GHz
Sawtooth
ARMv8.6‑A[ 53]
4-wide
Yes
LITTLE
8
2*128b
5
No
128 + 64
4 MiB
No
4x Sawtooth
?
2.02 GHz
Nvidia
Denver [ 56] [ 57] 2014
ARMv8‑A
2-wide hardwareVLIW
13
Not if the hardwareVLIW .
Direct+
No
7
28
No
No
128 + 64
2 MiB
No
2
?
?
Denver 2 [ 58] 2016
ARMv8‑A
?
13
Not if the hardwareVLIW .
Direct+
"Super" Nvidia's own implementation
?
16
No
No
128 + 64
2 MiB
No
2
?
?
Carmel
2018
ARMv8.2‑A
?
Direct+
?
12
No
No
128 + 64
2 MiB
(4 MiB @ 8 cores)
2 (+ 8)
6.5-7.4
?
Cavium
ThunderX [ 59] [ 60] 2014
ARMv8-A
2-wide
9[ 60]
Yes[ 59]
Two-level
?
28
No
No
78 + 32[ 61] [ 62]
16 MiB[ 61] [ 62]
No
8–16, 24–48
?
?
ThunderX2 [ 63] (ex. Broadcom Vulcan[ 64]
2018[ 65]
ARMv8.1-A[ 66]
4-wide[ 67] [ 68]
?
Yes[ 69]
Multi-level
?
?
16[ 70]
SMT4
No
32 + 32
256 KiB[ 71]
1 MiB[ 71]
16–32[ 71]
?
?
Marvell
ThunderX3
2020[ 72]
ARMv8.3+[ 72]
8-wide
?
Yes
Multi-level
?
7
7[ 72]
SMT4[ 72]
?
64 + 32
512 KiB
90 MiB
60
?
?
Applied
Micro
Helix
2014
?
?
?
?
?
?
?
40 / 28
No
No
32 + 32 (per core;[ 73]
256 KiB shared
1 MiB/core
2, 4, 8
?
?
X-Gene
2013
?
4-wide
15
Yes
?
?
?
40[ 74]
No
No
8 MiB
8
4.2
?
X-Gene 2
2015
?
4-wide
15
Yes
?
?
?
28[ 75]
No
No
8 MiB
8
4.2
?
X-Gene 3[ 75]
2017
?
?
?
?
?
?
?
16
No
No
?
?
32 MiB
32
?
?
Qualcomm
Kryo
2015
ARMv8-A
?
?
Yes
Two-level?
"big" or "LITTLE"
?
14[ 76]
No
No
32+24[ 77]
0.5–1 MiB
2+2
6.3
?
Kryo 200
2016
ARMv8-A
2-wide
11–12
Yes
Two-level
big
7
14 / 11 / 10 / 6[ 78]
No
No
64 + 32/64?
512 KiB/Gold Core
No
4
?
1.8–2.45 GHz
2-wide
8
No
0
Conditional+
LITTLE
2
8–64? + 8–64?
256 KiB/Silver Core
4
?
1.8–1.9 GHz
Kryo 300
2017
ARMv8.2-A
3-wide
11–13
Yes
Two-level
big
8
10[ 78]
No
No
64+64[ 78]
256 KiB/Gold Core
2 MiB
2, 4
?
2.0–2.95 GHz
2-wide
8
No
0
Conditional+
LITTLE
28
16–64? + 16–64?
128 KiB/Silver
4, 6
?
1.7–1.8 GHz
Kryo 400
2018
ARMv8.2-A
4-wide
11–13
Yes
Yes
big
8
11 / 8 / 7
No
No
64 + 64
512 KiB/Gold Prime
256 KiB/Gold
2 MiB
2, 1+1, 4, 1+3
?
2.0–2.96 GHz
2-wide
8
No
0
Conditional+
LITTLE
2
16–64? + 16–64?
128 KiB/Silver
4, 6
?
1.7–1.8 GHz
Kryo 500
2019
ARMv8.2-A
4-wide
11–13
Yes
Yes
big
8 / 7
No
?
512 KiB/Gold Prime
256 KiB/Gold
3 MiB
2, 1+3
?
2.0–3.2 GHz
2-wide
8
No
0
Conditional+
LITTLE
2
?
128 KiB/Silver
4, 6
?
1.7–1.8 GHz
Kryo 600
2020
ARMv8.4-A
4-wide
11–13
Yes
Yes
big
6 / 5
No
?
64 + 64
1024 KiB/Gold Prime
512 KiB/Gold
4 MiB
2, 1+3
?
2.2–3.0 GHz
2-wide
8
No
0
Conditional+
LITTLE
2
?
128 KiB/Silver
4, 6
?
1.7–1.8 GHz
Falkor[ 79] [ 80]
2017[ 81]
"ARMv8.1-A features";[ 80] AArch64 only (not 32-bit ) [ 80]
4-wide
10–15
Yes
Yes
?
8
10
No
24 KiB
88[ 80]
500KiB
1.25MiB
40–48
?
?
Samsung
M1[ 82] [ 83]
2016
ARMv8-A
4-wide
13[ 84]
Yes[ 85]
96
big
8
14
No
No
64 + 32
2 MiB[ 86]
No
4
?
2.6 GHz
M2[ 82] [ 83]
2017
ARMv8-A
4-wide
100
Two-level
big
10
No
No
64 + 64
2 MiB
No
4
?
2.3 GHz
M3[ 84] [ 87]
2018
ARMv8.2-A
6-wide
15
Yes
228
Two-level
big
12
10
No
No
64 + 64
512 KiB per core
4096KB
4
?
2.7 GHz
M4[ 88]
2019
ARMv8.2-A
6-wide
15
Yes
228
Two-level
big
12
8 / 7
No
No
64 + 64
512 KiB per core
3072KB
2
?
2.73 GHz
M5[ 89]
2020
ARMv8.2-A
6-wide
Yes
228
Two-level
big
7
No
No
64 + 64
512 KiB per core
3072KB
2
?
2.73 GHz
Fujitsu
A64FX [ 90] [ 91] 2019
ARMv8.2-A
4/2-wide
7+
Yes
Yes
n/a
8+
2*512b[ 92]
7
No
No
64 + 64
8MiB per 12+1 cores
No
48+4
?
1.9 GHz+
HiSilicon
TaiShan V110[ 93]
2019
ARMv8.2-A
4-wide
?
Yes
n/a
8
7
No
No
64 + 64
512 KiB per core
1 MiB per core
?
?
?
Company
Core
Released
Revision
Decode
Pipeline Out-of-order
Branch
big.LITTLE role
Exec. ports
SIMD
Fab nm )
Simult. MT
L0 cache
L1 cache Instr + Data KiB )
L2 cache
L3 cache
Core
Speed per core (DMIPS/ [ note 1]
Clock rate
ARM part number (in the main ID register)
ARMv9-A
Company
Core
Released
Revision
Decode
Pipeline depth
Out-of-order execution
Branch
big.LITTLE role
Exec. ports
SIMD
Fab nm )
Simult. MT
L0 cache
L1 cache Instr + Data KiB )
L2 cache
L3 cache
Core
Speed per core (DMIPS/ [ note 1]
Clock rate
ARM part number (in the main ID register)
Have it
Entries
Arm Holdings
Cortex-A510
May 2021
ARMv9-A
3 instructions decoded per cycle
8 stages
No
N/A (does not support out-of-order execution)
Advanced techniques similar to larger cores, specifics not disclosed
LITTLE
3 execution ports
Yes (supports SIMD instructions)
5nm (common for SoCs using Cortex-A510)
No
N/A
32 or 64 KB each
Configurable, typically 128 KB to 512 KB
N/A
Typically paired with Cortex-A710 in configurations (e.g., 1+3)
Not explicitly stated, but performance uplift of 35% over A55
Up to 2.85 GHz (varies by implementation)
Not specified in search results
Arm Holdings
Cortex-A710
May 2021
ARMv9.0-A
5 instructions decoded per cycle
10 stages
Yes
13 entries
Enhanced with larger structures and better accuracy
big
5 execution ports
Yes
5nm
Yes
Not specified
64/128 KiB each
256/512 KiB
Optional, up to 16 MiB
Typically 1+3+4 (big.LITTLE)
Not specified in results
Up to 3.0 GHz (approx.)
Not specified in results
Arm Holdings
Cortex-A715
June 2022
ARMv9-A
5 instructions decoded per cycle
15 stages
Yes
128 entries
Advanced branch prediction capabilities
big
4 execution ports
Yes
4nm
Yes
Not specified
64 KiB each
1 MiB
16 MiB (in certain configurations)
1+3+4 or similar setups
Not specified, but designed for high efficiency
Up to 2.8 GHz
Not specified
Arm Holdings
Cortex-X2
May 2021
ARMv9-A
6 instructions per cycle
15 stages
Yes
2048 entries
Advanced, with improved accuracy
big
3 execution ports
Yes
5nm
Yes
Not specified
64 KiB each
1 MiB
8 MiB
1+3+4 (X2+A710+A510)
Not specified
Up to 3.2 GHz
Not specified
Arm Holdings
Cortex-X3
June 2022
ARMv9.0-A
1 instruction per cycle
15 stages
Yes
128 entries
Advanced branch prediction capabilities
big
4 execution ports
Yes
4nm
Yes
Not specified
64 KiB each
1 MiB
16 MiB
1+3+4 or up to 8+4
Not specified
Up to 3.6 GHz
Not specified
ARMv9-M
ARMv9-R
See also
Notes
^ a b c d e As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.
References
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^ "Arm Unveils the Cortex-A78: When Less Is More" . WikiChip Fuse . 26 May 2020. Retrieved 28 May 2020 .^ Ltd, Arm. "Cortex-A78" . ARM Developer . Retrieved 28 May 2020 . ^ a b c d e "Introducing the Arm Cortex-X Custom program" . community.arm.com . Retrieved 28 May 2020 .^ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: The Move to 64-bit" . AnandTech. Retrieved 3 July 2014 . ^ a b c d e f g h i Lal Shimpi, Anand (31 March 2014). "Apple's Cyclone Microarchitecture Detailed" . AnandTech. Retrieved 3 July 2014 . ^ Dixon-Warren, Sinjin (20 January 2014). "Samsung 28nm HKMG Inside the Apple A7" . Chipworks. Archived from the original on 6 April 2014. Retrieved 3 July 2014 . ^ Lal Shimpi, Anand (17 September 2013). "The iPhone 5s Review: A7 SoC Explained" . AnandTech. Retrieved 3 July 2014 . ^ a b c d e f g h i j Ho, Joshua; Smith, Ryan (2 November 2015). "The Apple iPhone 6s and iPhone 6s Plus Review" . AnandTech. Retrieved 13 February 2016 . ^ "Apple had shifted the microarchitecture in Hurricane (A10) from a 6-wide decode from to a 7-wide decode" . AnandTech. 5 October 2018.^ a b c d "Apple A10 Fusion" . system-on-a-chip.specout.com . Retrieved 1 October 2016 .[permanent dead link ^ a b c d e "Measured and Estimated Cache Sizes" . AnandTech. 5 October 2018.^ a b "Apple A11 New Instruction Set Extensions" (PDF) . Apple Inc. 8 June 2018.^ a b "Apple A12 Pointer Authentication Codes" . Jonathan Levin, @Morpheus. 12 September 2018. Archived from the original on 10 October 2018. Retrieved 8 October 2018 .^ a b "A13 has ARMv8.4, apparently (LLVM project sources, thanks, @Longhorn)" . Jonathan Levin, @Morpheus. 13 March 2020.^ "The Apple A13 SoC: Lightning & Thunder" . AnandTech. 16 October 2019.^ "The A13's Memory Subsystem: Faster L2, More SLC BW" . AnandTech. 16 October 2019.^ a b c d e f "llvm-project/llvm/lib/Target/AArch64/AArch64.td at main - llvm/llvm-project - GitHub" . github.com . Retrieved 3 July 2023 .^ "Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14" . AnandTech. 10 November 2020.^ Frumusanu, Andrei. "Apple Announces The Apple Silicon M1: Ditching x86 – What to Expect, Based on A14" . anandtech.com . Retrieved 25 November 2020 . ^ Stam, Nick (11 August 2014). "Mile High Milestone: Tegra K1 "Denver" Will Be First 64-bit ARM Processor for Android" . NVidia. Archived from the original on 12 August 2014. Retrieved 11 August 2014 . ^ Gwennap, Linley. "Denver Uses Dynamic Translation to Outperform Mobile Rivals" . The Linley Group . Retrieved 24 April 2015 . ^ Ho, Joshua (25 August 2016). "Hot Chips 2016: NVIDIA Discloses Tegra Parker Details" . Anandtech. Retrieved 25 August 2016 . ^ a b De Gelas, Johan (16 December 2014). "ARM Challenging Intel in the Server Market" . Anandtech. Retrieved 8 March 2017 . ^ a b De Gelas, Johan (15 June 2016). "Investigating the Cavium ThunderX" . Anandtech. Retrieved 8 March 2017 . ^ a b "64-bit Cortex Platform To Take on x86 Servers in the Cloud" . electronic design. 5 June 2014. Retrieved 7 February 2015 .^ a b "ThunderX_CP™ Family of Workload Optimized Compute Processors" (PDF) . Cavium. 2014. Retrieved 7 February 2015 .^ "A Look at Cavium's New High-Performance ARM Microprocessors and the Isambard Supercomputer" . WikiChip Fuse . 3 June 2018. Retrieved 17 June 2019 .^ "⚙ D30510 Vulcan is now ThunderX2T99" . reviews.llvm.org .^ Kennedy, Patrick (7 May 2018). "Cavium ThunderX2 256 Thread Arm Platforms Hit General Availability" . Retrieved 10 May 2018 . ^ "⚙ D21500 [AARCH64] Add support for Broadcom Vulcan" . reviews.llvm.org .^ Hayes, Eric (7 April 2014). "IDC HPC USER FORUM" (PDF) . hpcuserforum.com . ^ "The Linley Group – Processor Conference 2013" . linleygroup.com .^ "ThunderX2 ARM Processors- A Game Changing Family of Workload Optimized Processors for Data Center and Cloud Applications – Cavium" . cavium.com .^ "Broadcom Announces Server-Class ARMv8-A Multi-Core Processor Architecture" . Broadcom. 15 October 2013. Retrieved 11 August 2014 .^ a b c Kennedy, Patrick (9 May 2018). "Cavium ThunderX2 Review and Benchmarks a Real Arm Server Option" . Serve the Home. Retrieved 10 May 2018 . ^ a b c d Frumusanu, Andrei (16 March 2020). "Marvell Announces ThunderX3: 96 Cores & 384 Thread 3rd Gen Arm Server Processor" . ^ Ganesh T S (3 October 2014). "ARMv8 Goes Embedded with Applied Micro's HeliX SoCs" . AnandTech. Retrieved 9 October 2014 . ^ Morgan, Timothy Prickett (12 August 2014). "Applied Micro Plots Out X-Gene ARM Server Future" . Enterprisetech. Retrieved 9 October 2014 . ^ a b De Gelas, Johan (15 March 2017). "AppliedMicro's X-Gene 3 SoC Begins Sampling" . Anandtech. Retrieved 15 March 2017 . ^ "Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute" . Qualcomm. 2 September 2015. Retrieved 6 September 2015 .^ Frumusanu, Ryan Smith, Andrei. "The Qualcomm Snapdragon 820 Performance Preview: Meet Kryo" . {{cite web }}: CS1 maint: multiple names: authors list (link )^ a b c Smith, Andrei Frumusanu, Ryan. "The Snapdragon 845 Performance Preview: Setting the Stage for Flagship Android 2018" . Retrieved 11 June 2018 . {{cite news }}: CS1 maint: multiple names: authors list (link )^ Shilov, Anton (16 December 2016). "Qualcomm Demos 48-Core Centriq 2400 SoC in Action, Begins Sampling" . Anandtech. Retrieved 8 March 2017 . In 2015, Qualcomm teamed up with Xilinx and Mellanox to ensure that its server SoCs are compatible with FPGA-based accelerators and data-center connectivity solutions (the fruits of this partnership will likely emerge in 2018 at best). ^ a b c d Cutress, Ian (20 August 2017). "Analyzing Falkor's Microarchitecture" . Anandtech. Retrieved 21 August 2017 . The CPU cores, code named Falkor, will be ARMv8.0 compliant although with ARMv8.1 features, allowing software to potentially seamlessly transition from other ARM environments (or need a recompile). The Centriq 2400 family is set to be AArch64 only, without support for AArch32: Qualcomm states that this saves some power and die area, but that they primarily chose this route because the ecosystems they are targeting have already migrated to 64-bit. Qualcomm's Chris Bergen, Senior Director of Product Management for the Centriq 2400, stated that the majority of new and upcoming companies have started off with 64-bit as their base in the data center, and not even considering 32-bit, which is a reason for the AArch64-only choice here. [..] Micro-op cache / L0 I-cache with Way prediction [..] The L1 I-cache is 64KB, which is similar to other ARM architecture core designs, and also uses 64-byte lines but with an 8-way associativity. To software, as the L0 is transparent, the L1 I-cache will show as an 88KB cache. ^ Shrout, Ryan (8 November 2017). "Qualcomm Centriq 2400 Arm-based Server Processor Begins Commercial Shipment" . PC Per. Retrieved 8 November 2017 . ^ a b Ho, Joshua. "Hot Chips 2016: Exynos M1 Architecture Disclosed" . ^ a b Frumusanu, Andrei. "Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU" . ^ a b Frumusanu, Andrei (23 January 2018). "The Samsung Exynos M3 – 6-wide Decode with 50%+ IPC Increase" . Anandtech. Retrieved 25 January 2018 . ^ Frumusanu, Andrei. "Hot Chips 2016: Exynos M1 Architecture Disclosed" . Anandtech . Retrieved 29 May 2017 . ^ " . The Register ^ Frumusanu, Andrei. "Hot Chips 2018: Samsung's Exynos-M3 CPU Architecture Deep Dive" . anandtech.com . Retrieved 17 June 2019 . ^ Schor, David (14 January 2019). "Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End" . WikiChip Fuse . Retrieved 17 June 2019 . ^ Frumusanu, Andrei. "ISCA 2020: Evolution of the Samsung Exynos CPU Microarchitecture" . anandtech.com . Retrieved 24 January 2021 . ^ Fujitsu High Performance CPU for the Post-K Computer (PDF) , 21 July 2018, retrieved 16 September 2019 ^ Arm A64fx and Post-K: Game Changing CPU & Supercomputer for HPC and its Convergence of with Big Data / AI (PDF) , 3 April 2019, retrieved 16 September 2019 ^ "Fujitsu Successfully Triples the Power Output of Gallium-Nitride Transistors – Fujitsu Global" . fujitsu.com . Retrieved 23 November 2020 .^ Schor, David (3 May 2019). "Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen" . WikiChip Fuse . Retrieved 13 December 2019 .
Application ARM-based chips
Application
ARMv7-A
Cortex-A5 Cortex-A7
Allwinner A2x, A3x, A83T, H3, H8 NXP i.MX7 , QorIQ LS10xx , NXP i.MX6UL Broadcom BCM2836 , BCM23550Leadcore LC1813 , LC1860/C, LC1913, LC1960
Marvell Armada 1500 mini plus, PXA1920MediaTek MT65xxRockchip RK3126 Qualcomm Snapdragon 200 , 205, 208, 210, 212, 400 UNISOC SC7731E Cortex-A8 Cortex-A9
Actions ATM702x , ATM703x
Altera Cyclone V, Arria V/10
Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T86x Apple A5 , A5X Broadcom BCM21xxx, BCM28xxx Freescale i.MX6 HiSilicon K3V2 , 910's InfoTM iMAPx912
Leadcore LC1810, LC1811
Marvell Armada 1500 miniMediaTek MT65xxNvidia Tegra , 2 , 3 , 4i Nufront NuSmart 2816M, NS115, NS115M
Renesas EMMA EV2, R-Car H1, RZ/ARockchip RK292x , RK30xx , RK31xx Samsung Exynos 4 421x , 441x ST-Ericsson NovaThor
Telechips TCC8803
Texas Instruments OMAP 4 , Sitara AM4xxx
VIA WonderMedia WM88x0, 89x0
Xilinx Zynq-7000
ZiiLABS ZMS-20, ZMS-40 Cortex-A15 Cortex-A17 Others ARMv7-A
Apple A6 , A6X , S1 , S1P , S2 , S3 Broadcom Brahma-B15Marvell P4JQualcomm Snapdragon S1, S2, S3, S4 Plus, S4 Pro, 600, 800 (Scorpion , Krait )
ARMv8-A
Application
ARMv8-A
Cortex-A35 Cortex-A53
Actions GT7, S900, V700
Allwinner A133, A64, H5, H64, R18 Altera Stratix 10
Amlogic S9 Family, T96x Broadcom BCM2837 EZchip TILE-Mx100HiSilicon Kirin 620 , 650, 655, 658, 659 , 930, 935 Marvell Armada PXA1928, Mobile PXA1908/PXA1936MediaTek MT673x , MT675x , MT6761V , MT6762 /V , MT6763T , MT6765 /G/H , MT6795 , MT8161, MT8163, MT8165, MT8732, MT8735, MT8752 NXP ARM S32 , QorIQ LS1088, LS1043 , i.MX8M Qualcomm Snapdragon 215 , 410, 412, 415, 425, 427, 429, 430, 435, 439, 450 , 610, 615, 616, 617, 625, 626, 630 Renesas RZ/V2M
Rockchip RK3328, RK3368, RK3562, RK3566
Samsung Exynos 7570, 7578, 7580, 7870, 7880 Texas Instruments Sitara AM6xxx
UNISOC SC9820E , SC9832E, SC9860/GV
Xilinx ZynqMP Cortex-A57 Cortex-A72
AWS Graviton Broadcom BCM2711 HiSilicon Kirin 950, 955 , Kunpeng 916 MediaTek MT6797/D/T/X , MT8173, MT8176, MT8693 MStar 6A938Qualcomm Snapdragon 650, 652, 653 Rockchip RK3399 NXP QorIQ LS2088 , QorIQ LS1046A , QorIQ LX2160A , QorIQ LS1028A , i.MX8 Cortex-A73
Qualcomm Snapdragon 460 , 632, 636, 660, 662, 665, 680, 685 , 6s 4G Gen 1 , 835 Samsung Exynos 7872, 7884, 7885, 7904, 9609, 9610, 9611 HiSilicon Kirin 710 , 960 , 970 MediaTek MT6771/V , MT6799 , MT8183, MT8788 Amlogic S922X Others ARMv8-A
ARMv8.1-A
ARMv8.2-A
Cortex-A55 Cortex-A75
Qualcomm Snapdragon 670 , 710, 712 , 845 , 850 Samsung Exynos 9820, 9825 MediaTek MT6769H/T/V/Z , MT6768, MT6779V UNISOC T310 , T606, T610, T615, T616, T618, T619, T620, T700, T710, T7200, T7225, T7250, T7255, T7280, T740 Cortex-A76
Allwinner A733 Google Tensor HiSilicon Kirin 810, 820 , 980, 985 , 990 Qualcomm Snapdragon 480(+) , 675, 678 , 720G, 730(G), 732G, 765(G), 768G , 855(+), 860 , 7c (Gen 2), 8c, 8cx (Gen 2) Microsoft SQ1, SQ2
MediaTek MT6781, MT6785V, MT6789 , MT6833V/P, MT6853V/T , MT6873, MT6875 , MT8192 , Dimensity 6020, 6080, 6100+, 6300(+), 6400 Rockchip RK3588sSamsung Exynos 990 UNISOC T750 , T760, T765, T770, T820, T8100, T8200, T8300, T9100 Cortex-A77 Cortex-A78
Google Tensor G2MediaTek MT6877, MT6878 , MT6879, MT6891, MT6893 , Dimensity 7020, 7025 (Ultra), 7030, 7050, 7300 (Energy/Pro/Ultimate/Ultra/X), 7400(X) , 8000, 8020, 8050, 8100, 8200 (Ultimate/Ultra) , Kompanio 900T, 1200, 1380, 1300T Qualcomm Snapdragon 4 Gen 1, 4(s) Gen 2 , 695 , 6 Gen 1, 6(s) Gen 3 , 778G(+), 780G, 782G , 888(+) Samsung Exynos 1080, 1280, 1330, 1380, 1480 , 2100 Cortex-X1 Neoverse N1 Others
Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A78C, Cortex-X1C, Neoverse E1 ARMv8.2-A
ARMv8.3-A
ARMv8.4-A
ARMv8.5-A
ARMv8.6-A
ARMv8.7-A
ARMv9.0-A
ARMv9.2-A
Embeddedmicrocontrollers
Cortex-M0
Cypress PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M
Infineon XMC1000
Nordic nRF51
NXP LPC1100, LPC1200
nuvoTon NuMicro
Sonix SN32F700
STMicroelectronics STM32 F0
Toshiba TX00
Vorago VA108x0 Cortex-M0+
Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+
Holtek HT32F52000
Microchip (Atmel) SAM C2, D0, D1, D2, DA, L2, R2, R3
NXP LPC800, LPC11E60, LPC11U60
NXP (Freescale) Kinetis E, EA, L, M, V1, W0
Raspberry Pi RP2040
Renesas Synergy S1
Silicon Labs (Energy Micro) EFM32 Zero, Happy
STMicroelectronics STM32 L0 Cortex-M1
Altera FPGAs Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
Microsemi (Actel ) FPGAs Fusion, IGLOO/e, ProASIC3L, ProASIC3/EXilinx FPGAs Spartan-3, Virtex-2-3-4 Cortex-M3
Actel SmartFusion, SmartFusion 2
Analog Devices ADuCM300
Cypress PSoC 5000, 5000LP, FM3
Fujitsu FM3
Holtek HT32F
Microchip (Atmel) SAM 3A, 3N, 3S, 3U, 3X
NXP LPC1300, LPC1700, LPC1800
ON Semiconductor Q32M210
Silicon Labs Precision32
Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant
STMicroelectronics STM32 F1, F2, L1
Texas Instruments F28, LM3, TMS470, OMAP 4
Toshiba TX03 Cortex-M4
Microchip (Atmel) SAM 4L, 4N, 4S
NXP (Freescale) Kinetis K, W2
Renesas RA4W1, RA6M1, RA6M2, RA6M3, RA6T1 Cortex-M4F
Cypress 6200, FM4
Infineon XMC4000
Microchip (Atmel) SAM 4C, 4E, D5, E5, G5
Microchip CEC1302
Nordic nRF52
NXP LPC4000, LPC4300
NXP (Freescale) Kinetis K, V3, V4
Renesas Synergy S3, S5, S7
Silicon Labs (Energy Micro) EFM32 Wonder
STMicroelectronics STM32 F3, F4, L4, L4+, WB
Texas Instruments LM4F/TM4C, MSP432
Toshiba TX04 Cortex-M7F
Microchip (Atmel) SAM E7, S7, V7
NXP (Freescale) Kinetis KV5x, i.MX RT 10xx, i.MX RT 11xx, S32K3xx
STMicroelectronics STM32 F7, H7 Cortex-M23
GigaDevice CD32E2xx
Microchip (Atmel) SAM L10, L11, and PIC 32CM-LE 32CM-LS
Nuvoton M23xx family, M2xx family, NUC1262, M2L31
Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2 Cortex-M33F
Analog Devices ADUCM4
Dialog DA1469x
GigaDevice GD32E5, GD32W5
Nordic nRF91, nRF5340, nRF54
NXP LPC5500 , i.MX RT600
ON RSL15
Renesas RA4, RA6
ST STM32 H5, L5, U5, WBA
Silicon Labs Wireless Gecko Series 2 Cortex-M35P Cortex-M55F Cortex-M85F
Real-time
Classic ARM-based chips
Classic
ARM7
Atmel SAM7L, SAM7S, SAM7SE, SAM7X, SAM7XC , AT91CAP7 , AT91M, AT91R
Cirrus Logic PS7xxx, EP7xxx
Mediatek MT62xx
NXP LPC2100, LPC2200, LPC2300, LPC2400 , LH7
STMicroelectronics STR7 ARM9
Aspeed AST2400
Atmel SAM9G, SAM9M, SAM9N, SAM9R, SAM9X, SAM9XE, SAM926x , AT91CAP9
Cirrus Logic EP9xxx
Freescale i.MX1x, i.MX2x
Nuvoton NUC900
NXP LPC2900 , LPC3000 , LH7A
Philips Nexperia PNX4008
Rockchip RK27xx, RK28xx
Samsung S3C24xx
STMicroelectronics Nomadik STn881x
STMicroelectronics STR9
Texas Instruments OMAP 1 , AM1x , DaVinci
VIA WonderMedia WM8505/8650
ZiiLABS ZMS-05 ARM11 ARMv2a ARMv4 ARMv5TE
Intel/Marvell XScale
Marvell Sheeva, Feroceon, Jolteon, MohawkFaraday FA606TE, FA616TE, FA626TE, FA726TE
