List of Intel graphics processing units
The Intel Graphics badge
This article contains information about Intel 's GPUs (see Intel Graphics Technology ) and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.[ 1] [ 2]
First generation
Intel's first generation GPUs:
Graphics
Launch
Market
Chipset
Code name
Device ID[ 3]
RAMDACclock (MHz )
Pixel pipelines
Shader model (vertex /pixel )
API support
Memory bandwidth (GB/s )
DVMT (MB )
Hardware acceleration
Direct3D
OpenGL
OpenCL
MPEG-2
VC-1
AVC
i740
1998
Desktop
stand-alone
Auburn
7800
220
1
3.0 (SW) / No
5.0
1.1
No
0.8
2–8
Optional external MPEG-2 decoder via Video Module Interface
No
No
i752
1999
Portola
1240
250
6.0 (full) 8.0 (some features, no hardware shaders)
0.8(PC100 )–1.067(PC133 ) 1.067(AGP 4× for AIMM )
8–16
MC
3D graphics with Direct AGP
810
Whitney
7121
230
32
810-DC100
7123
810E 810E2
7125
2000
815 815E 8925G 815EG
Solano
1132
6.0 (full) 9.0 (some features, no hardware shaders)
Second generation
Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.
Third generation
Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support.
Gen4
The last generation of motherboard integrated graphics. Full hardware DirectX 10 support starting with GMA X3500.
Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle.
Graphics
Launch
Market
Code name
Chipset
Device ID [ 3]
Core renderclock (MHz )
Execution units
Shader model (vertex /pixel )
API support[ 13]
Memory bandwidth (GB/s )
DVMT (MB )
Hardware acceleration
Direct3D
OpenGL
OpenCL
MPEG-2
VC-1
AVC
GMA 3000
2006
Desktop
Lakeport
946GZ
2972
667[ 14] [ 15]
8[ 14] [ 16]
3.0 (SW) / 2.0
9.0c FL 9_1
1.5Windows 2.1macOS 2.1Linux ES 2.0Linux
No
10.6
256
MC[ 8]
No
No
Broadwater
Q963
2992
Q965
12.8
GMA X3000
G965
29A2
3.0
384
Full[ 8]
MC + (LF −WMV9 only)
GMA X3500
2007
Bearlake
G35
2982
4.0
10.0 FL 10_0
MC + LF
GMA X3100
Mobile
Crestline
GL960
2A02 2A12
400[ 17]
8.5
MC + (LF −WMV9 only)
GLE960
GM965
500[ 17]
10.7
GME965
GMA 4500
2008
Desktop
Eaglelake
B43
2E42 2E92
533
10
2.1 ES 2.0Linux
12.8 (DDR2) 17 (DDR3)[ 18]
1720
MC + LF
MC + LF
Q43
2E12
Q45
GMA X4500
G41
2E32
800
G43
2E22
GMA X4500HD
G45
Full
Full
GMA 4500MHD
Mobile
Cantiga
GL40
2A42
400[ 19]
GS40
GM45
533[ 19]
GS45
GM47
640
Gen5
Integrated graphics chip moved from motherboard into the processor.
Improved gaming performance
Can access CPU's cache
Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.[ 20]
Hierarchical-Z compression and fast Z clear[ 21]
Gen6
Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle.[ 20]
Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction.[ 20]
The entire GPU shares a sampler and an ROP .[ 20]
Gen7
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Gen7.5
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions.
Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.
Gen8
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions is one per 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
Each Subslice contains 8 EUs and a sampler (4 tex/clk[ 47] ), and has 64 KB shared memory.
Intel Quick Sync Video
For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT .
Gen9
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter (eighth in Apollo Lake ) of the FP32 FLOPS.
Each Subslice contains 8 EUs (two of which are disabled in GT1) and a sampler (4 tex/clk), and has 64 KB shared memory.
Intel Quick Sync Video
For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.
WDDM 2.2 support with Windows Mixed Reality begins with KabyLake-based GPUs.[ 54]
Gen11
1 FP32 ALUs : EUs : Subslices
Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS.
Each Subslice contains 8 EUs and a sampler (4 tex/clk), and has 64 KB shared memory.
Intel Quick Sync Video
For Windows 10, the total system memory that is available for graphics use is half the system memory.
No eDRAM.
Gen12
Intel Xe is a GPGPU and dGPU product line first released in 2020, in the mobile Tiger Lake line and Rocket Lake , Alder Lake and Raptor Lake line.
1 FP32 ALUs: EUs: Subslices
Gen 12.5
Model[ 73] [ 74]
Launch
Code name(s)
Process
Transistors (billion)
Die size (mm2 )
Core config[ a]
Cache
Core clock (MHz )[ b]
Fillrate [ c] [ d]
Memory
Processing power (TFLOPS )
TDP
Bus interface
L1
L2
Pixel (GP /s)
Texture (GT /s)
Type
Size
Bandwidth (GB /s)
Bus width
Clock (MT/s )
Bfloat16
Single precision
Double precision
Data Center GPU Max 1100
Jan 10, 2023
Xe-HPC (Ponte Vecchio)
Multiple[ 75]
100
1280
7168:448:0:56:448:448
28 MB
204 MB
10001550
0
448.0694.4
HBM2E
48 GB
1228.8
3072-bit
3200
352
14.33622.221
300 W
PCIe 5.0 x16
Data Center GPU Max 1350
abandoned
14336:896:0:112:896:896
56 MB
408 MB
7501550
672.01388.8
96 GB
2457.6
6144-bit
704
21.50444.442
450 W
Data Center GPU Max 1550
Jan 10, 2023
16384:1024:0:128:1024:1024
64 MB
408 MB
9001600
921.61638.4
128 GB
3276.8
8192-bit
832
29.49154.423
600 W
^ shading cores (ALU):texture mapping units (TMU):render output units (ROP):ray tracing units:tensor cores (XMX):execution Units
^ Boost values (if available) are stated below the base value in italic .
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed .
Gen 12.7
Desktop
Overview of Intel Arc Alchemist GPUs
Branding and Model[ 76]
Launch
MSRP (USD)
Code name
Process
Transistors (billion)
Die size (mm2 )
Core config [ a]
L2 cache
Clock rate (MHz )[ b]
Fillrate
Memory
Processing power (TFLOPS )
TDP
Bus interface
Pixel (GP /s)
Texture (GT /s)
Type
Size (GB )
Bandwidth (GB /s)
Bus width
Clock (MT/s )
Half precision (base)
Single precision (base)
Double precision (base)
Arc 3
A310
Sep 28, 2022
$110
ACM-G11 (DG2-128)
TSMC N6
7.2
157
6 Xe cores 768:32:16:6 (192:96:2)
4 MB
2000 2000
32
64
GDDR6
4 GB
124
64-bit
15500
6.144
3.072
n/a
75 W
PCIe 4.0 x8
A380
Jun 14, 2022
$139
8 Xe cores 1024:64:32:8 (256:128:2)
2000 2050
6465.6
128131.2
6 GB
186
96-bit
8.1928.3968
4.0964.1984
n/an/a
Arc 5
A580
Oct 10, 2023
$179
ACM-G10 (DG2-512)
21.7
406
24 Xe cores 3072:192:96:24 (768:384:6)
8 MB
1700 1700
163.2
326.4
8 GB
512
256-bit
16000
20.890
10.445
n/a
175 W
PCIe 4.0 x16
Arc 7
A750
Oct 14, 2022
$289
28 Xe cores 3584:224:112:28 (896:448:7)
16 MB
2050 2400
229.6268.8
393.6460.8
29.388834.4064
14.694417.2032
n/an/a
225 W
A770 8GB
$329
32 Xe cores 4096:256:128:32 (1024:512:8)
2100 2400
268.8307.2
537.6614.4
34.406439.3216
17.203219.6608
n/an/a
A770 16GB
$349
16 GB
560
17500
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution units: render slices)
^ Boost values (if available) are stated below the base value in italic .
Mobile
Overview of Intel Arc Alchemist GPUs for mobile devices
Branding and Model[ 77]
Launch
Code name
Process
Transistors (billion)
Die size (mm2 )
Core config[ a] [ b]
L2 cache
Core clock (MHz )[ c]
Fillrate [ d]
Memory
Processing power (TFLOPS )
TDP
Bus interface
Pixel (GP /s)
Texture (GT /s)
Type
Size
Bandwidth (GB /s)
Bus width
Clock (MT/s )
Half precision
Single precision
Double precision
Arc 3
A350M
Mar 30, 2022
ACM-G11 (DG2-128)
TSMC N6
7.2
157
6 Xe cores 768:48:24:6 (96:96:2)
4 MB
11502200
27.652.8
55.2105.6
GDDR6
4 GB
112
64-bit
14000
3.53286.7584
1.76643.3792
0.44160.8448
25–35 W
PCIe 4.0 ×8
A370M
8 Xe cores 1024:64:32:8 (128:128:2)
15502050
49.665.6
99.2131.2
6.34888.3968
3.17444.1984
0.79361.0496
35–50 W
Arc 5
A530M
Q3 2023
ACM-G12 (DG2-256)
12 Xe cores 1536:96:48:12 (192:192:3)
8 MB
1300
4 GB 8 GB
224
128-bit
65–95 W
A550M
Q2 2022
ACM-G10 (DG2-512)
21.7
406
16 Xe cores 2048:128:64:16 (256:256:4)
9001700
57.6108.8
115.2217.6
8 GB
7.372813.9264
3.68646.9632
0.92161.7408
60–80 W
A570M
Q3 2023
ACM-G12 (DG2-256)
1300
75–95 W
Arc 7
A730M
Q2 2022
ACM-G10 (DG2-512)
21.7
406
24 Xe cores 3072:192:96:24 (384:384:6)
12 MB
11002050
105.6196.8
211.2393.6
12 GB
336
192-bit
13.516825.1904
6.758412.5952
1.68963.1488
80–120 W
PCIe 4.0 ×16
A770M
32 Xe cores 4096:256:128:32 (512:512:8)
16 MB
16502050
211.2262.4
422.4524.8
16 GB
512
256-bit
16000
27.033633.5872
13.516816.7936
3.37924.1984
120–150 W
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution units: render slices)
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed .
^ Boost values (if available) are stated below the base value in italic .
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed , number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
Workstation
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution Units: render slices)
^ Boost values (if available) are stated below the base value in italic .
^ Pixel fillrate is calculated as the lowest of three numbers: number of ROPs multiplied by the base core clock speed, number of rasterizers multiplied by the number of fragments they can generate per rasterizer multiplied by the base core clock speed, and the number of streaming multiprocessors multiplied by the number of fragments per clock that they can output multiplied by the base clock rate.
^ Texture fillrate is calculated as the number of texture mapping units (TMUs) multiplied by the base (or boost) core clock speed .
Battlemage based
Branding and Model
Launch
MSRP (USD)
Codename
Process
Transistors (billion)
Die size (mm2 )
Core config[ a]
L2 cache
Clock rate (MHz )[ b]
Fillrate
Memory
Processing power (TFLOPS )
TDP
Bus interface
Pixel (GP /s)
Texture (GT /s)
Type
Size (GB )
Bandwidth (GB /s)
Bus width
Clock (MT/s )
Half precision
Single precision
Double precision
XMX Half precision
Arc 5
B580
Dec 13, 2024
$249
BMG-G21
TSMC N5
19.6
272
20 Xe-cores 2560:160:80:20 (160:160:5)
18 MB
2670 2850
213.6228
427.2456
GDDR6
12 GB
456
192-bit
19000
27.34129.184
13.67014.592
1.7091.824
218.726233.472
190 W
PCIe 4.0 x8
B570
Jan 16, 2025
$219
18 Xe-cores 2304:144:80:18 (144:144:5)
13.5 MB
2500 2750
180198
360396
10 GB
380
160-bit
19000
23.04025.344
11.52012.672
1.4401.584
184.320202.752
150 W
^ Shading cores (ALU): texture mapping units (TMU): render output units (ROP): ray tracing units (tensor cores (XMX): execution units: render slices)
^ Boost values (if available) are stated below the base value in italic .
PowerVR based
See also
Notes
Acronyms
The following acronyms are used throughout the article.
Full hardware acceleration techniques
Intel graphic processing units employ the following techniques in hardware acceleration of digital video playback.
Calculation
The raw performance of integrated GPU, in FLOPS , can be calculated as follows:
GPU
FLOPS
FP16
FP32
FP64
Gen4 (GMA 3, 4)
-
(clock speed) * (# of FP32 ALUs)
-
Gen5 (HD Graphics)
Gen6 (HD Graphics 2000, 3000)
(clock speed) * 2 * (# of FP32 ALUs)
Gen7 (HD Graphics 2500, 4000 ~ 5200)
(clock speed) * (# of FP32 ALUs) / 2
Gen8 (HD Graphics 5300 ~ 6300)
(clock speed) * 2 * (# of FP32 ALUs) * 2
Gen9 (HD Graphics 5xx, 6xx)
Gen11
For example, the HD Graphics 3000 is rated at 125 GFLOPS,[ 109] which is consistent with the formula (12 * 4 * 2 * 1,300 MHz).
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