Low-power FSM synthesis

This article includes a list of general references, but it lacks sufficient corresponding inline citations. Please help to improve this article by introducing more precise citations. (April 2015) (Learn how and when to remove this message)

Finite-state machines (FSMs) are widely used to implement control logic in various applications such as microprocessors, digital transmission, digital filters and digital signal processing. Even for designs containing a good number^{[clarification needed]} of datapath elements, the controller occupies a sizeable portion. As the devices are mostly portable and hand-held, reducing power dissipation has emerged as the primary concern of today's VLSI designers. While the datapath elements can be shut down when they are not being used, controllers are always active. As a result, the controller consumes a good amount^{[clarification needed]} of system power. Thus, power-efficient synthesis of FSM has come up as a very important problem domain, attracting a lot of research. The synthesis method must be able to reduce both dynamic power and leakage power consumed by the circuit.

An FSM can be defined as a quintuplet that consists of a set of primary inputs, a set of primary outputs, a set of states, a next-state function and an output function. The next-state function maps the present-state and the primary inputs to a next-state; the output function maps the primary inputs and present-state onto the primary outputs. Any deterministic sequential function can be represented by the use of this model. A FSM can be separated into two parts viz., combinational circuit and memory.

The optimal synthesis of finite-state machines is an important step in digital design. The three basic steps involved in the FSM synthesis are:

1. State minimization: the number of states is reduced by recognizing the equivalent states that are present in the FSM and merging them. When state minimization is possible, it is deemed that the resulting FSM will be easier to build
2. State encoding: The complexity of the combinational logic depends on the assignment of codes to each of the states in the FSM. This is also referred to as state assignment. A good state assignment reduces the cost of implementation significantly. There are many encoding techniques such as gray coding, binary coding, and one-hot coding.
3. Determination of Boolean functions for next-state and output functions: The Boolean equations can be obtained by a two-level structure or random-logic by an interconnection of logic primitives. In either case, Boolean minimization, logical partitioning and decomposition are essential for an efficient realization

In CMOS circuits, power is dissipated in a gate when the gate output changes from 0 to 1 or from 1 to 0. Optimizing for low average power consumption in digital CMOS circuits is in most of the cases motivated by reducing the problems related to either heat generated by the integrated circuit (IC) or by limited power supply resources, as in portable battery-operated equipment.

The most common approach for low power FSM synthesis is to divide the FSM into two or more sub-FSMs in which at any given instant only one of these is active. The power minimization problem can be considered at various levels viz., algorithmic, architectural, logic and circuit levels. The dynamic power consumed in synchronous CMOS circuits is given by:

${\displaystyle P=V_{DD}^{2}f\sum _{i}{\alpha _{i}}{C_{i}},}$ where ${\displaystyle \alpha _{i}}$ is the probability of a signal transmission within a clock period at node ${\displaystyle i}$, ${\displaystyle C_{i}}$ is the switched capacitance, ${\displaystyle V_{DD}}$ is the supply voltage and ${\displaystyle f}$ is the clock frequency.

1. Partitioning of the FSM physically increases the area of the circuit but reduces the dynamic power consumed.
2. In the synthesis, state encoding plays an important role for efficient realization. The Boolean distance between the codes is minimized with a high transition probability, using a probability descriptor of the FSM.
3. In input disabling precomputational based approach, datapath units which are combinational logic are turned off to disable the values to the input signals. This reduces the dynamic power
4. In sequential circuits, gate-clock techniques such as power gating are used to disable the clock signal to the parts of the system that are idle
5. For complex microprocessors, floating point units and cache memory blocks are turned off when idle. This method is called dynamic power management

The amount of power that is saved by partitioning the FSM is mainly determined by how good the partitioning algorithm can cluster strongly connected states together in sub-FSMs and by how large the cost is, in terms of power, to make a state transition from one sub-FSM to another.

1. http://www.nptel.ac.in/courses/106103016/9
2. L. Benini, G. De Micheli, State assignment for low power dissipation, IEEE Journal on Solid State Circuits (1994) 32–40
3. W. Noeth, R. Kolla., Spanning tree-based state encoding for low power dissipation, Design Automation and Test in Europe (1999)
4. Sambhu Nath Pradhan, M. Tilak Kumar, and Santanu Chattopadhyay. 2011. Low power finite state machine synthesis using power-gating. Integr. VLSI J. 44, 3 (June 2011), 175–184
5. Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, and C. L. Liu. 1996. Low power realization of finite state machines—a decomposition approach. ACM Trans. Des. Autom. Electron. Syst. 1, 3 (July 1996)