Princeton Application Repository for Shared-Memory Computers (PARSEC) is a benchmark suite composed of multi-threaded emerging workloads that is used to evaluate and develop next-generation chip-multiprocessors. It was collaboratively created by Intel and Princeton University to drive research efforts on future computer systems.[1][2] Since its inception the benchmark suite has become a community project that is continued to be improved by a broad range of research institutions.[3] PARSEC is freely available and is used for both academic and non-academic research.[4][5][6]
Background
The introduction of chip-multiprocessors required computer manufacturers to rewrite software for the first time to take advantage of parallel processing capabilities, including rewriting existing systems for testing and development.[2][7] At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors became commonly available software developers were not willing to rewrite any mainstream programs, which means hardware manufacturers did not have access to any programs for test and development purposes that represented the expected real-world program behavior accurately. This posed a hen-and-egg problem that motivated a new type of benchmark suite with parallel programs that could take full advantage of chip-multiprocessors.
PARSEC was created to break this circular dependency. It was designed to fulfill the following five objectives:[8]
Focuses on multithreaded applications
Includes emerging workloads
Has a diverse selection of programs
Workloads employ state-of-art techniques
The suite supports research
Traditional benchmarks that were publicly available before PARSEC were generally limited in their scope of included application domains or typically only available in an unparallelized, serial version. Parallel programs were only prevalent in the domain of High-Performance Computing and on a much smaller scale in business environments.[9]Chip-multiprocessors however were expected to be heavily used in all areas of computing such as with parallelized consumer applications.
Workloads
The PARSEC Benchmark Suite is available in version 2.1, which includes the following workloads:[10]
^Rabaey, Jan M.; Burke, Daniel; Lutz, Ken; Wawrzynek, John (July–August 2008), "Workloads of the Future"(PDF), IEEE Design & Test of Computers, IEEE, archived from the original(PDF) on 2011-08-07, retrieved 2010-02-12
^Bienia, Christian; Kumar, Sanjeev; Singh, Jaswinder Pal; Li, Kai (October 2008), "The PARSEC Benchmark Suite: Characterization and Architectural Implications", Proceedings of the 17th international conference on Parallel architectures and compilation techniques, Association for Computing Machinery, New York, NY, USA
^Bienia, C.; Kumar, S.; Kai Li (2008). "PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors". 2008 IEEE International Symposium on Workload Characterization. p. 47. doi:10.1109/IISWC.2008.4636090. ISBN978-1-4244-2777-2. S2CID1805881.
