RISC-V assembly language
RISC-V assembly language is a low-level programming language that is used to produce object code for the RISC-V class of processors. Assembly languages are closely tied to the architecture's machine code instructions, allowing for precise control over hardware. Assemblers include GNU Assembler and LLVM. KeywordsReserved keywords of RISC-V assembly language.
Mnemonics and opcodesEach instruction in the RISC-V assembly language is represented by a mnemonic which often combines with one or more operands to translate into one or more bytes known as an opcode. RegistersRISC-V processors feature a set of registers that serve as storage for binary data and addresses during program execution. These registers are categorized into integer registers and floating-point registers. Instruction typesRISC-V instructions use variable-length encoding. Extensions:
Floating-point instructionsRISC-V assembly language includes instructions for a floating-point unit (FPU). SIMD instructionsThese largely perform the same operation in parallel on many values. Program flowThe RISC-V assembly has conditional branch instructions based on comparison: Examples.section .text
.globl _start
_start:
lui a1, %hi(msg) # load msg(hi)
addi a1, a1, %lo(msg) # load msg(lo)
jalr ra, puts
2: j 2b
.section .rodata
msg:
.string "Hello World\n"
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