RISC-V instruction listings

The RISC-V instruction set refers to the set of instructions that RISC-V compatible microprocessors support. The instructions are usually part of an executable program, often stored as a computer file and executed on the processor.

RISC-V Integer Instructions

The table below contains a list of the RV Integer Instructions.^[1] The integer instruction set is divided in the base I part of the ISA that comes in a 32 bit RV32 and 64 bit RV64 version and M, B and Zicond extensions. There is also an A extension for atomic instructions and F and D instructions for floating point operations.

RV Integer (pseudo) Instructions
Instruction	Name	Format	Extension	RV64
lb	Load Byte	rd, imm12(rs)	I
lh	Load Half	rd, imm12(rs)	I
lw	Load Word	rd, imm12(rs)	I
ld	Load Double	rd, imm12(rs)	I	x
lbu	Load Byte (U)	rd, imm12(rs)	I
lhu	Load Half (U)	rd, imm12(rs)	I
lwu	Load Word (U)	rd, imm12(rs)	I	x

sb	Store Byte	rs1, imm12(rs2)	I
sh	Store Half	rs1, imm12(rs2)	I
sw	Store Word	rs1, imm12(rs2)	I
sd	Store Double	rs1, imm12(rs2)	I	x

li	Load Immediate	rd, imm	I^{[note 1]}
lui	Load Upper Immediate	rd, imm20	I
auipc	Add Upper Immediate to Program Counter	rd, imm20	I

mv	MoVe	rd, rs	I^{[note 2]}
sext.b	move Sign EXTended least significant Byte	rd, rs	B
sext.h	move Sign Extended least significant Half	rd, rs	B
sext.w	move Sign EXTended least significant Word	rd, rs	I^{[note 2]}	x
zext.b	move Zero EXTended least significant Byte	rd, rs	I^{[note 2]}
zext.h	move Zero EXTended least significant Half	rd, rs	B
zext.w	move Zero EXTended least significant Word	rd, rs	B^{[note 2]}	x
rev8	move with REVersed byte order	rd, rs	B
czero.eqz	move Conditional on EQual to Zero or ZERO	rd, rs1, rs2	Zicond
czero.nez	move Conditional on Not Equal to Zero or ZERO	rd, rs1, rs2	Zicond

addi	ADD Immediate	rd, rs, imm12	I
add	ADD	rd, rs1, rs2	I
sh1add	SHift1 ADD	rd, rs1, rs2	B
sh2add	SHift2 ADD	rd, rs1, rs2	B
sh3add	SHift3 ADD	rd, rs1, rs2	B
add.wu	ADD Word(U to double)	rd, rs1, rs2	B	x
sh1add.wu	SHift1 Word(U in double) Add to double	rd, rs1, rs2	B	x
sh2add.wu	SHift2 Word(U in double) Add to double	rd, rs1, rs2	B	x
sh3add.wu	SHift3 Word(U in double) Add to double	rd, rs1, rs2	B	x
addiw	ADD Word to Word Immediate	rd, rs, imm12	I	x
addw	ADD Word	rd, rs1, rs2	I	x
sub	SUBtract	rd, rs1, rs2	I
subw	SUBtract Word	rd, rs1, rs2	I	x
neg	NEGative.	rd, rs	I^{[note 2]}
negw	Negative Word	rd, rs	I^{[note 2]}	x

mul	MULtiply	rd, rs1, rs2	M
mulw	MULtiply Word	rd, rs1, rs2	M	x
mulh	MULtiply High part	rd, rs1, rs2	M
mulhu	MULtiply High Part Unsigned	rd, rs1, rs2	M
mulhsu	MULtiply High Part Unsigned Signed	rd, rs1, rs2	M
div	DIVide	rd, rs1, rs2	M
divu	DIVide (U)	rd, rs1, rs2	M
rem	REMainder	rd, rs1, rs2	M
remu	REMainder (U)	rd, rs1, rs2	M

min	MINimum	rd, rs1, rs2	B
max	MAXimum	rd, rs1, rs2	B
minu	MINimum (U)	rd, rs1, rs2	B
maxu	MAXimum (U)	rd, rs1, rs2	B

seqz	Set EQual to Zero	rd, rs	I^{[note 2]}
snez	Set Not Equal to Zero	rd, rs	I^{[note 2]}
slti	Set Less Than Immediate	rd, rs, imm12	I
slt	Set Less Than	rd, rs1, rs2	I
sltiu	Set Less Than Immediate (U)	rd, rs, imm12	I
sltu	Set Less Than (U)	rd, rs1, rs2	I
bexti	Bit Extract Immediate	rd, rs, imm5/6	B
bext	Bit Extract	rd, rs1, rs2	B

andi	AND Immediate	rd, rs, imm12	I
and	AND	rd, rs1, rs2	I
andn	AND Not	rd, rs1, rs2	B
bclri	Bit CLeaR Immediate	rd, rs, imm5/6	B
bclr	Bit CLeaR	rd, rs1, rs2	B
ori	OR Immediate	rd, rs, imm12	I
or	OR	rd, rs1, rs2	I
orn	OR Not	rd, rs1, rs2	B
bseti	Bit SET Immediate	rd, rs, imm5/6	B
bset	Bit SET	rd, rs1, rs2	B
xori	eXclusive OR Immediate	rd, rs, imm12	I
xor	eXclusive OR	rd, rs1, rs2	I
xnor	Not XOR	rd, rs1, rs2	B
binvi	Bit INVert Immediate	rd, rs, imm5/6	B
binv	Bit INVert	rd, rs1, rs2	B
not	NOT	rd, rs	I^{[note 2]}
orc.b	OR Combine within Bytes	rd, rs	B

slli	Shift Left Logical Immediate	rd, rs, imm5/6	I
sll	Shift Left Logical	rd, rs1, rs2	I
slliw	Shift Left Logical Word Immediate	rd, rs, imm5	I	x
sllw	Shift Left Logical Word	rd, rs1, rs2	I	x
slli.wu	Shift Left Logical Word (U in double) Immediate	rd, rs, imm5/6	I	x
srli	Shift Right Logical Immediate	rd, rs, imm5/6	I
srl	Shift Right Logical	rd, rs1, rs2	I
srliw	Shift Right Logical Word Immediate	rd, rs, imm5	I	x
srlw	Shift Right Logical Word	rd, rs1, rs2	I	x
srai	Shift Left Arith Immediate	rd, rs, imm5/6	I
sra	Shift Right Arithmetic	rd, rs1, rs2	I
sraiw	Shift Left Arith Word Immediate	rd, rs, imm5	I	x
sraw	Shift Right Arithmetic Word	rd, rs1, rs2	I	x
rori	ROtate Right Immediate	rd, rs, imm5/6	B
ror	ROtate Right	rd, rs1, rs2	B
rol	ROtate Left	rd, rs1, rs2	B
roriw	ROtate Right Immediate Word	rd, rs, imm5	B	x
rorw	ROtate Right Word	rd, rs1, rs2	B	x
rolw	ROtate Left Word	rd, rs1, rs2	B	x

clz	Count Leading Zeros	rd, rs	B
clzw	Count Leading Zeros in Word	rd, rs	B	x
ctz	Count Trailing Zeros	rd, rs	B
ctzw	Count Trailing Zeros in Word	rd, rs	B	x
cpop	Count POPulation of 1s	rd, rs	B
cpopw	Count POPulation of 1s in Word	rd, rs	B	x

j	Jump	label	I^{[note 2]}
jal	Jump And Link	rd, imm20	I
jr	Jump Register	rs [, imm12]	I^{[note 2]}
jalr	Jump And Link Register	rd rs [, imm12]	I
call	CALL	symbol	I^{[note 3]}
tail	TAIL call	symbol	I^{[note 4]}
ret	RETurn	-

beq	Branch ==	rs1, rs2, label	I
bne	Branch !=	rs1, rs2, label	I
blt	Branch <	rs1, rs2, label	I
bgt	Branch >	rs1, rs2, label	I^{[note 2]}
bge	Branch >=	rs1, rs2, label	I
ble	Branch <=	rs1, rs2, label	I^{[note 2]}
bltu	Branch < (U)	rs1, rs2, label	I
bgtu	Branch > (U)	rs1, rs2, label	I^{[note 2]}
bgeu	Branch >= (U)	rs1, rs2, label	I
bleu	Branch <= (U)	rs1, rs2, label	I^{[note 2]}

nop	NoOPeration	-	I
ecall	Environment CALL	-	I
ebreak	Environment BREAK	-	I

Remarks

^ Assembler macro, for immediates needing less than 12 bit expands to addi rd zero imm
^ ^a ^b ^c ^d ^e ^f ^g ^h ⁱ ^j ^k ^l ^m ⁿ ^o Pseudo Instruction. Expands to single instruction.
^ Assembler macro clobbering ra. Interacts with the loader symbol relocation. Expands to jal ra, imm or auipc ra, imm; jalr ra, ra imm combination
^ Assembler macro, may clobber t1. Interacts with the loader symbol relocation. Expands to jal zero imm or auipc t1, imm; jalr zero t1, imm combination
^ Pseudo instruction clobbering ra. Expands to jal zero, ra, 0